Polycide refers to a structure which includes a layer of doped polycrystalline silicon (polysilicon) and an overlying metal silicide layer. Polycide is used, for example, to form gate electrodes in field effect transistors (FETs). FIG. 1 is a top view of an n-channel FET 100 which includes source region 101, drain region 102, polycide gate electrode 103, and field oxide 107. FIG. 2a is a cross sectional view of FET 100 along plane 2a--2a of FIG. 1. FIG. 2b is a cross sectional view of FET 100 along plane 2b--2b of FIG. 1. FIGS. 2a and 2b also show gate oxide 106 and silicon semiconductor substrate 110.
Polycide gate electrode 103 is typically fabricated by depositing a layer of polysilicon 103a over field oxide 107 and gate oxide 106, conductively doping polysilicon layer 103a, depositing a layer of metal silicide 103b over polysilicon layer 103a, and performing one or more masking and etching steps. Polycide gate electrode 103 can also be formed by depositing and conductively doping polysilicon layer 103a, depositing a metal layer over polysilicon layer 103a, and performing a heating step in which part, but not all, of polysilicon layer 103a is consumed to form a metal silicide layer over the remaining polysilicon layer.
Polysilicon layer 103a provides an appropriate work function to gate electrode 103 and an appropriate threshold voltage to FET 100 according to the work function and the voltage threshold parameters desired. Silicide layer 103b provides a low contact resistance with polysilicon layer 103a (compared, for example, to an aluminum gate electrode) and reduces the overall sheet resistance of gate electrode 103.
There are several drawbacks associated with polycide gate electrode 103. As illustrated in FIG. 2b, silicide layer 103b typically has bad step coverage. In the areas where underlying polysilicon layer 103a undergoes a change in height, i.e., at portions 111 and 112, silicide layer 103b is deposited to a lesser thickness than the remainder of silicide layer 103b. Portions 111 and 112 have a high resistance compared to the rest of silicide layer 103b, thereby undesirably increasing the resistance of gate electrode 103.
Another problem with FET 100 is that topography changes at the surface of the FET structure can cause depth of focus difficulties when performing conventional lithography steps. This loss of resolution requires the use of a wider line size.
A further problem with polycide gate 103 is that silicide layer 103b exerts stress on polysilicon layer 103a. If this stress becomes large enough, damage to the underlying gate oxide 106 may occur.
Another problem is specific to polycides fabricated by tungsten chemical vapor deposition (CVD). A tungsten fluoride gas (WF.sub.6) in a silane (SiH.sub.4) carrier is typically used during the CVD fabrication of tungsten silicide (WSi.sub.x, where x.gtoreq.2). Some of the fluorine in the tungsten fluoride gas may be present in the tungsten silicide after the tungsten silicide is deposited. This fluorine can diffuse through the underlying polysilicon layer 103a to gate oxide 106 during subsequent thermal cycling, thereby degrading the dielectric properties of gate oxide 106.
Another problem can occur when etching unwanted portions of a polycide structure. For example, if polycide gate 103 of FIG. 2b is anisotropically etched, undesired spacers, referred to as silicide stringers, may be formed adjacent to step portions 111 and 112 because the vertical thickness of silicide layer 103b is too thick to be completely removed at these locations. FIG. 3 illustrates silicide stringers 121-122. Silicide stringers 121-122 can undesirably create leakage paths between gate electrodes. To eliminate silicide stringers 121-122, the silicide etch is sometimes prolonged. However, because the selectivity of the silicide etchant to polysilicon is typically less than 1:1, the silicide etchant will attack the underlying polysilicon layer 103a faster than silicide layer 103b. Thus, any attempt to prolong the silicide etch to remove silicide stringers 121-122 may result in the removal of an excessive amount of polysilicon layer 103a. If the prolonged silicide etch extends through polysilicon layer 103a, the gate oxide layer 106 may be attacked. The selectivity of the silicide etchant to silicon oxide is typically in the vicinity of 5:1 to 1:1. The silicide etchant can therefore potentially reach and undesirably destroy portions of gate oxide 106.
It would therefore be desirable to have a structure and method of forming a polycide gate which eliminates or mitigates the above-described shortcomings of prior art polycide structures.